Current Issue : October - December Volume : 2015 Issue Number : 4 Articles : 6 Articles
Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects\non chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate\npower consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel\narea-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and\ncombinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been\nmodified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in\ncombinational logic during shift mode.The new gating scan cells also mitigate the number of transitions during shift and capture\ncycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power\nduring capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17%total average power compared to\nconventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures....
The speed and power consumption of flash analog to digital converter (ADC) is governed by design of thermometer to binary (T2B) encoders used in it. In this study, ROM, Wallace tree, Fat tree and multiplexer (MUX) based encoders are compared for their performance. Power delay product analysis and bubble error analysis results suggest that the MUX based encoder may be preferred for use in flash ADCs. An improved new MUX based encoder is proposed which utilizes small 2:1 MUXs arranged in a more regular structure for the improvement in speed and power. The design of improved 15 to 4-bit MUX based encoder shows 19.1% and 14.2% improvement in speed and power respectively over conventional MUX based encoder....
The growing complexity and higher time-to-market pressure make the functional verification of modern large scale hardware\nsystemsmore challenging. These challenges bring the requirement of a high quality testbench that is capable of thoroughly verifying\nthe design. To reveal a bug, the testbench needs to activate it by stimulus, propagate the erroneous behaviors to some checked points,\nand detect it at these checked points by checkers. However, current dominant verification approaches focus only on the activation\naspect using a coverage model which is not qualified and ignore the propagation and detection aspects. Using a new metric, this\npaper qualifies the testbench by mutation analysis technique with the consideration of the quality of the stimulus, the coverage\nmodel, and the checkers. Then the testbench is iteratively refined according to the qualification feedback. We have conducted\nexperiments on two designs of different scales to demonstrate the effectiveness of the proposed method in improving the quality\nof the testbench....
This paper presents a competitive alternative to conventional passive spiral grounded inductor by realising a newly designed CMOS grounded active inductor circuit. The realised grounded active inductor has been used to implement a low frequency band pass filter design. The simulation of the proposed grounded active inductor and implementation of band pass filter in low frequency domain are carried out by using Cadence Virtuoso UMC 180 nm technology by spectre simulator....
The adaptive computationally-scalable motion estimation\nalgorithm and its hardware implementation allow the\nH.264/AVC encoder to achieve efficiencies close to optimal in\nreal-time conditions. Particularly, the search algorithm\nachieves results close to optimumeven if the number of search\npoints assigned to macroblocks is strongly limited and varies\nwith time. The architecture implementing the algorithmdeveloped\nand reported previously takes at least 674 clock cycles to\ninterpolate and load reference area, and the number cannot be\ndecreased without decreasing the search range. This paper\nproposes some optimizations of the architecture to increase\nthe maximal throughput achieved by the motion estimation\nsystem even four times. Firstly, the chroma interpolation follows\nthe search process, whereas the luma interpolation precedes\nit. Secondly, the luma interpolator computes 128 instead\nof 64 samples per each clock cycle. Thirdly, the number of onchip\nmemories keeping interpolated reference area is increased\naccordingly to 128. Fourthly, somemodules previously\nworking at the base frequency are redesigned to operate at\nthe doubled clock. Since the on-chip memories do not store\nfractional-pel chroma samples, their joint size is reduced from\n160.44 to 104.44 kB. Additional savings in the memory size\nare achieved by the sequential processing of two referencepicture\nareas for each macroblock. The architecture is verified\nin the real-time FPGA hardware encoder. Synthesis\nresults show that the updated architecture can support\n2160p@30fps encoding for 0.13 ?m TSMC technology with\na small increase in hardware resources and some losses in the\ncompression efficiency. The efficiency is improved when processing\nsmaller resolutions....
A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of\nsteep roll-off high stopband rejection (>20 dB) and low noise figure (<6 dB) provides a wide tuning frequency span (1ââ?¬â??2.04GHz) to\naccept desirable signals and reject close interfering signals. The process variation aware design approach demonstrates robustness\nof the BPF after calibration from process variations, operating in 1.04GHz tuning frequency span: almost zero deviation on center\nfrequency, an average maximum deviation 1.16 dB on a nominal pass band gain of 55.6 dB, and an average maximum deviation\n1.06MHz on a nominal bandwidth of 12.3MHz....
Loading....